FIG. 1 is a schematic representation of a data system such as a magnetic recording medium. In FIG. 1, a sequence of user data is input to an Error Correcting Coder (ECC) 20. An encoder 25 receives k-bit blocks of output b(i) from the ECC 20 and produces m-bit blocks c(i), which are referred to as codewords. The rate of the encoder 25 is thus k/m. The encoder 25 may include an application-specific integrated circuit (ASIC). The encoder 25 outputs the codeword c(i) to a 1/(1⊕D2) precoder 30. The ECC 20, the encoder 25, and the precoder 30 receive, encode, and process data in a digital domain. The encoder 25 and the precoder 30 may be combined into one control block capable of encoding and precoding the ECC output b(i), or the precoder may be omitted all together.
The output of the precoder 30, x(i) passes through a channel having one or more filters. FIG. 1 shows a cascade of channel filters 35, 40 denoted by (1−D2) and (a+bD+cD2). The output of the filters 35, 40 is corrupted by additive noise, n(i) such that the received sequence r(i) is defined by r(i)=z(i)+n(i). Based on the received sequence r(i), a Viterbi detector 50, for example, generates a detected sequence {circumflex over (x)} (i), which is a reproduction of the input x(i) to the channel filters 35, 40. Next, bits {circumflex over (x)} (i)s are filtered by a filter (1⊕D2) 55, which is an inverse of the precoder 30, to generate g(i). The filter (1⊕D2) 55 may be provided within the detector 50 as one unit. The output g(i) of the filter 55, is decoded by a decoder 60 to produce a decoded sequence d(i), which is a reproduction of the ECC output sequence, b(i). An ECC decoder 65 receives the output sequence d(i).
If x(i)≠{circumflex over (x)}(i), then it is determined that a channel error has occurred at location (time) i. Further, if b(i)≠d(i), then it is determined that a decoder error has occurred at location (time) i.
In general, in magnetic recording, encoders and decoders perform one or more of the following tasks:                1) enforcing Run Length Limited (RLL) conditions,        2) enhancing system performance (distance), and        3) providing clock recovery information (non-zero samples.)        
For task No. 3 mentioned above, there are clocks within the system that must be synchronized. A downstream clock must be expecting a symbol when it is received. Clock drift is a problem associated with the clocks not being synchronized. That is, when a part of the system is expecting a bit to be received, the bit is in the middle of transmission. To accomplish synchronization, a clock looks at the received non-zero symbols and synchronizes its pulses with the receipt of non-zero symbols. Hence, for the purpose of clock recovery, it is beneficial that there be a sufficiently large number of “non-zero”s traveling through the channel.
In generating codewords c(i), the encoder 25 may consider clock recovery. In this case, the encoder 25 produces a sufficiently large number of “1”s for transmission through the channel. FIG. 2A shows an encoder map for an encoder having a rate 64/65 with 64 user bits being received and 65 coded bits c(i) being produced. The encoder map shown in FIG. 2A produces at least 33 “1”s in every 65 bit codeword. To do this, the encoder counts the number of “1”s in every 64 bit sequence of ECC output b(i). If the number of “1”s is more than 32, then the encoder adds a “0” at the end of the block as bit c64. Thus, (c0, c1, c2, . . . c63)=(b1, b2, b3, . . . b64).
When the encoder counts the number of “1”s in the 64 bit sequence of ECC output, it is possible that the number of “1”s will be less than or equal to 32. In this case, the 64 incoming bits are changed to the compliment thereof, such that a received “1” is changed to an output “0”, and a received “0” is changed to an output “1. ” To produce the codeword, a “1” is added to the end as bit c64 to the 64 bit block (c0, c1, c2, . . . c63).
The decoder takes the opposite action as the encoder. A map for the decoder is shown in FIG. 2B. With this decoder, if g64 is a “0”, then the decoder outputs bits g0 through g63 as bits d0 through d63. On the other hand, if g64 is a “1”, then the decoder outputs the compliment of bits g0 through g63 as bits d0 through d63.
It should be apparent that bits c64 and g64 are very important. They determine the output for 64 bits of data. In traveling through the channel, the data can be corrupted. If g64 is improperly received at the decoder, a 1 bit error will propagate into a 64 bit error. The operation of the decoder is depended on the map used by the encoder.